The testing of very large scale integrated logic and storage circuits on chips, of which electronic controls, processors and other data processing systems consist, is based to a considerable degree on the accessibility of the storage elements on the chips. It is in connection with these components that problems arise, since digital systems necessitate a very high error coverage and the testing of very large scale integrated circuit structures consumes much time and is very expensive in view of the circuit density of VLSI (Very Large Scale Integration) chips. Data processing systems, such as microprocessors, consist of or comprise highly complicated chips which have to be tested taking account of a vast number of states bistable storage elements may assume and of an even vaster number of state sequences such processor storage elements pass through during the execution of program routines.
Assuming a micro instruction to be a finite functional value, then the testing of the generally well-specified and well-defined function of a micro instruction, such as the setting of bistable switches indicating the states of an arithmethic and logic unit (ALU) after execution of an ADD micro instruction, poses problems that are not too difficult to resolve. Serious problems are encountered however if all possible secondary functions of the ADD micro instruction are to be tested, such as whether the state of a bistable switch, for instance that indicative of bus requests occurring during the execution of the ADD microinstruction, has changed or not.
Secondary functions generally require a large number of bistable switches or storage elements which are associated with the data flow and the control logic of the microprocessor. Generally, such storage elements are not directly accessible for test purposes, not even by special micro instructions, without changing the respective current states of the bistable switches or storage elements used for state indication.
Testable very large scale integrated logic structures and system architectures frequently utilize LSSD (Level Sensitive Scan Design) rules, according to which a logic subsystem, for instance, is signal level dependent if and only if the response in the steady state to an input signal change is independent of circuit and bus delays within that logic subsystem (cf. "A Logic Design Structure for LSI Testability" by E. B. Eichelberger--Proceedings of the Design Automation Conference, No. 14, June 20 to 22, 1977, New Orleans, La., pp. 462 to 468).
Based on these LSSD design rules, the various storage elements on a chip are monitored and adjusted by linking the master-slave flip-flops, forming part of the logic and positioned between the logic stages, in the test mode as one or several shift register chains through which the test patterns are shifted into and result patterns are shifted from the very logic.
Such shift register chains also permit shifting complete flip-flop or register status information of complex logic stages, limited with regard to their packaging, such as a chip or a module.
Such a register concept has the added advantage that only relatively few input/output connections are required and that a high degree of flexibility is obtained between the various packaging levels if all first packaging level shift register chains are connected to a common second packaging level shift register chain, and so on, without affecting the logic design within the chips.
As the storage elements of a processor are almost invariably designed as shift register stages, the secondary functions can either be tested by an integrated maintenance and service processor or by a connected separate tester such that before and after execution of the micro instruction to be tested the contents of the bistable storage elements, connected for testing in the form of shift registers, are shifted into the maintenance and service processor or the tester, by means of which the difference in states is compared with predetermined desired values.
Another considerable improvement of the diagnostic capability of micro instruction tests during the exchange of data and instructions between processing units and processors may be obtained by applying the test procedures to even tighter functional values, such as the clocking steps of the micro instruction to be tested. This would lead to a considerably improved error coverage of automatic tests.
However, the afore-mentioned test methods have the disadvantage that they require the states stored in a very large nunber of bistable circuit elements to be transferred at very high speeds, which would have to be effected by the maintenance and service processor or a factory tester unsuitable for such application because of their slow test circuits and their serial shift mechanism. Apart from this, the clocking speed of the shift means cannot be increased further despite the high-speed technology of processor chips, since such a known shift chain comprises two slower networks, one of which extends from the processor or the processing unit to the maintenance and service processor and the other from the maintenance and service processor to the processor (cf. FIG. 1, lines 14 and 13).
Data processing systems generally comprise parallel high-speed system buses interconnecting several units, such as the processors 9, 10 . . . n, the main storage 3, the main storage control 4, the input/output device control 5 and, if necessary, the maintenance and service processor 6, as shown in FIG. 1. In known data processing systems, however, these system buses are normally not provided for direct access of the maintenance and service processor to the bistable elements of the processors which also contain status information, an exception being the test and diagnostic device for digital computers, as described in the European Patent Application No. 83 105 172.7. In that data processing system, the storage elements (flip-flops), interconnecting the logic subsystems during normal operation, are connected in the form of an addressable array for the error test and diagnostic mode, so that the unit to be tested receives from the maintenance and service processor on the fast system bus address information for controlling the individual storage elements of the array, test data for storage therein, and test control and clock information. Upon completion of testing, the result data of the logic subsystems are written into the connected storage elements. From these storage elements, connected in the form of an array, the result data are fed on the system bus to the maintenance and service processor with the aid of address and control information also transferred on that bus.
As the storage elements of the array consist only of master flip-flops, they may not be realized as usual in the form of shift registers comprising master-slave flip-flops, which is highly disadvantageous for many design concepts of data processing systems.
For data processing systems, whose storage elements are made up of master/slave flip-flops, the European Patent Application No. 83 112 339.3 describes a concept for the fast exchange of test data on the system bus, wherein the interface register stages, positioned between the system bus 8 and the processors 9 to n (cf. FIG. 1), are included in the shift register chain which is arranged in garland shape and whose start and end are connected during testing by a controlled switch 44 (cf. FIG. 2).
During testing, the input of test data and the output of result data, which in each case are effected on the system bus, overlap internal shift steps of the garland-shaped shift register chain.
Another disadvantage of known systems is that the test bus 13, 14 has only one core, so that line interruptions may lead to total failure of the test bus and thus of the data processing system, since the maintenance and service processor, in addition to test functions, generally performs system service functions by controlling, for instance, the system console from the display screen and the keyboard.
Serious problems in electronic data processing systems are caused above all by intermittent errors, especially if they are dependent on the system environment. Faulty supply networks, electrostatically charged floor coverings as well as high-frequency disturbance resulting from high-frequency generators of laboratory and manufacturing equipment installed in the vicinity of data processing systems are frequently the cause of intermittent errors. In such cases, micro instruction test programs fail as an instrument for systematically detecting errors and their causes.
Thus, it is the object of the invention to provide an arrangement of relatively simple design, by means of which electronic data processing equipment can be reliably error-tested at high speed also with respect to intermittent errors.
Thus, the invention has the advantage that electronic data processing systems with very large scale integrated circuits can be error-tested extremely economically, at high speed and very thoroughly.